Gate driving apparatus and display device
핵심 아이디어Key idea — 시프트 레지스터의 출력은 다음 단으로 넘기는 캐리로만 쓰고, 게이트 라인은 NMOS 3개로 된 출력 유닛이 전원(Vgh/VSS)에서 따로 구동하게 했다.The shift-register output is used only as the carry; the gate line is driven separately from Vgh/VSS by a three-NMOS outputting unit.
특허 요약Patent in brief — BOE의 GOA 게이트 구동 장치다. 각 단의 시프트 레지스터 출력(OUTPUT)이 게이트 라인을 직접 구동하지 않게 하고, 그 사이에 NMOS 3개(M21·M22·M23)로 된 출력 유닛을 넣어 Vgh/VSS로 게이트 라인을 구동한다. 패널 안에서 게이트 라인이 단락되어도 앞·뒤 단으로 가는 캐리 신호가 망가지지 않게 해 화면 전체 오동작을 막는 것이 목적이다([0005]–[0006]).BOE GOA gate driver. The shift-register OUTPUT no longer drives the gate line; an outputting unit of three NMOS TFTs (M21, M22, M23) drives it from Vgh/VSS. A short on a gate line inside the panel then cannot corrupt the carry to the neighbouring stages, which would otherwise break the whole screen ([0005]–[0006]).
검증 결론Verification result — 청구항 1의 효과는 재현됐다. 게이트 라인에 3 kΩ 누설 결함을 넣었을 때 발명의 캐리는 8.01 V로 유지되고, 종래 구조는 5.49 V로 떨어져 판정 기준 6 V를 넘지 못했다. 다만 정상 라인에서도 게이트 라인 하이는 7.05 V로, [0038]의 'Vgh를 출력한다'와 달리 Vgh보다 약 1 V 낮다.Claim 1's effect is reproduced: with a 3 kΩ leakage defect on the gate line the invention keeps the carry at 8.01 V, while the prior art drops to 5.49 V, below the 6 V criterion. Even on a healthy line the gate-line high is 7.05 V, about 1 V below Vgh, unlike [0038] which says Vgh is output.
해결하려는 과제Problem
종래 GOA는 시프트 레지스터 출력이 곧 게이트 라인 신호이면서 다음 단 입력과 이전 단 리셋으로도 쓰인다. 그래서 패널 안에서 게이트 라인 하나가 데이터선이나 공통전극과 단락되면 그 신호가 끌려 내려가고, 이웃 단이 줄줄이 오동작해 화면 전체가 깨진다.In a conventional GOA the shift-register output is the gate-line signal and also the next stage's input and the previous stage's reset. A single gate line shorted to a data or common line drags that signal down, the neighbouring stages misfire, and the whole screen fails.
공보 요약 원문 보기Show the publication abstract
It is an object of the present disclosure to provide a gate driving apparatus and a display device to settle an abnormal display in a full screen caused by an abnormality in signals output from a shift register, when a short-circuit occurs in wirings associated with gate lines within a liquid crystal panel.
청구항 1~3Claims 1–3
청구항Claim 1 독립independent
A gate driving apparatus comprising a plurality of gate driving units (2) connected in cascade, wherein each stage of the gate driving units (2) comprises a shift register unit (3) comprising a pulling-up driving module (11), a pulling-up module (12), a pullin… (펼치기)(more)
A gate driving apparatus comprising a plurality of gate driving units (2) connected in cascade, wherein each stage of the gate driving units (2) comprises a shift register unit (3) comprising a pulling-up driving module (11), a pulling-up module (12), a pullingdown controlling module (13), a pulling-down module (14), and a resetting module (15), wherein an input terminal of the pulling-down controlling module (13) is connected to a pulling-up node (PU), and an output terminal of the pulling-down controlling module (13) is connected to a pulling-down control node (PD-CN) in the pulling-down module (14), characterized in that each stage of the gate driving units (2) further comprises an outputting unit (4) for outputting a first power voltage (Vgh) or a second power voltage (VSS) to a respective gate line (gate1, gate2, ...), the outputting unit (4) comprising: a first outputting module (41) with a pulling-up control terminal (IN) connected to an output terminal (OUTPUT) of the shift register unit (3), for providing the first power voltage (Vgh) to an output terminal (OUT) of the outputting unit (4), in response to an output signal of the shift register unit (3); a second outputting module (42) with a terminal connected to a reset signal terminal (RET) of the shift register unit (3), for providing the second power voltage (VSS) to the output terminal (OUT) of the outputting unit (4), in response to a reset signal; a third outputting module (43) with a pullingdown control terminal (PD-CN signal) connected to the pulling-down control node (PD-CN) of the shift register unit (3), for providing the second power voltage (VSS) to the output terminal (OUT) of the outputting unit (4), in response to a voltage signal at the pulling-down control node (PD-CN), wherein a first power supply input terminal of the outputting unit (4) is connected to the first power voltage (Vgh), a second power supply input terminal of the outputting unit (4) is connected to the second power voltage (VSS), and the output terminal (OUT) of the outputting unit (4) is connected to the respective gate line (gate1, gate2, ...) as an output terminal (OUT) of the gate driving unit, so that the output terminal (OUTPUT) of the shift register unit (3) is not directly connected to the respective gate line (gate1, gate2, ...) to avoid a gate line shortedcircuit from affecting an output of the corresponding shift register unit (3); wherein the first outputting module (41) comprises a first thin film transistor (M21) whose gate is connected to the pulling-up control terminal (IN) of the outputting unit (4), whose source is connected to the first power supply input terminal (Vgh), and whose drain is connected to the output terminal (OUT) of the outputting unit (4); wherein the second outputting module (42) comprises a second thin film transistor (M22) whose gate is connected to the reset signal terminal (RET) of the outputting unit (4), whose source is connected to the output terminal (OUT) of the outputting unit (4), and whose drain is connected to the second power supply input terminal (VSS); wherein the third outputting module (43) comprises a third thin film transistor (M23) whose gate is connected to the pulling-down control terminal (PD-CN signal) of the outputting unit (4), whose source is connected to the output terminal (OUT) of the outputting unit (4), and whose drain is connected to the second power supply input terminal (VSS), the pulling-up module (12) comprises a fourth thin film transistor (M3) and a capacitor (C1), a gate of the fourth thin film transistor (M3) is connected to the pulling-up node (PU) and a first end of the capacitor (C1), a source of the fourth thin film transistor (M3) is connected to a clock signal input terminal (CLK), and a drain of the fourth thin film transistor (M3) is connected to the output terminal (OUTPUT) of the shift register and a second end of the capacitor (C1); the pulling-down controlling module (13) comprises a fifth thin film transistor (M6), a gate of the fifth thin film transistor (M6) is connected to the pulling-up node (PU), a source of the fifth thin film transistor (M6) is connected to the pulling-down control node (PD-CN), and a drain of the fifth thin film transistor (M6) is connected to the second power voltage input terminal (VSS); and the resetting module (15) comprises a sixth thin film transistor (M7) and a seventh thin film transistor (M9), a gate of the sixth thin film transistor (M7) is connected to the reset signal terminal (RET), a source of the sixth thin film transistor (M7) is connected to the pulling-up node (PU), and a drain of the sixth thin film transistor (M7) is connected to the second power voltage input terminal (VSS), and a gate of the seventh thin film transistor (M9) is connected to the reset signal terminal (RET), a source of the seventh thin film transistor (M9) is connected to the output terminal (OUTPUT) of the shift register, and a drain of the seventh thin film transistor (M9) is connected to the second power voltage input terminal (VSS).
청구항Claim 2 종속 → 1depends on 1
The gate driving apparatus of claim 1, characterized in that all of the thin film transistors (M21, M22, M23, M3, M6, M7, M9) are N-type thin film transistors.
청구항Claim 3 종속 → 1depends on 1
The gate driving apparatus of claim 1, characterized in that an input signal terminal (IN) of a first stage of shift register unit (S1) is connected to a frame start signal (STV), and a reset signal terminal (RET) of the first stage of shift register unit (S1)… (펼치기)(more)
The gate driving apparatus of claim 1, characterized in that an input signal terminal (IN) of a first stage of shift register unit (S1) is connected to a frame start signal (STV), and a reset signal terminal (RET) of the first stage of shift register unit (S1) is connected to an output terminal (OUTPUT) of a second stage of shift register unit (S2); an input signal terminal of a last stage of shift register unit is connected to an output terminal of a previous stage of shift register unit, and a reset signal terminal of the last stage of shift register unit is connected to the frame start signal (STV), or is connected to an output terminal of any stage of the shift register units except for its previous stage of shift register unit or an output terminal of an outputting unit; except for the first stage of shift register unit (S1) and the last stage of shift register unit, the input signal terminals of the remaining respective stage of shift register units are connected to the output terminals of their previous stage of shift register unit, and the reset signal terminals thereof are connected to the output terminals of next stage of shift register unit.
전체 4개 청구항 중 1~3항만 싣는다. 전체는 원문 PDF.Claims 1–3 of 4; the rest are in the source PDF.
회로 관련 주요 키워드Key circuit keywords
요약·청구항·명세서 전체에서 센 출현 횟수.Occurrence counts over abstract, claims and description.
해석Analysis
Claude (Opus 5.5)가 원문·도면·시뮬레이션 결과를 보고 작성했다.Written by Claude (Opus 5.5) from the text, drawings and simulation results.
회로Circuit
청구항 1: 시프트 레지스터 단(풀업 구동 11·풀업 12·풀다운 제어 13·풀다운 14·리셋 15) 뒤에 출력 유닛 4를 둔다. M21은 게이트=IN(=시프트 레지스터 OUTPUT), 소스=Vgh, 드레인=OUT이다. M22는 게이트=RET로 OUT을 VSS로 내리고, M23은 게이트=PD-CN으로 유지 구간에 OUT을 VSS로 잡는다. 청구항 2는 모든 TFT가 N형이라고 한정한다.Claim 1: after the shift-register stage (pull-up driving 11, pull-up 12, pull-down control 13, pull-down 14, reset 15) comes outputting unit 4. M21: gate = IN (= shift-register OUTPUT), source = Vgh, drain = OUT. M22 (gate = RET) pulls OUT to VSS; M23 (gate = PD-CN) holds OUT at VSS. Claim 2 makes every TFT N-type.
동작Operation
시프트 레지스터 n이 하이를 내면 다음 단으로 캐리가 넘어가는 동시에 M21이 켜져 게이트 라인이 Vgh 쪽으로 충전된다. 다음 단 출력(RET)이 오면 M22가 OUT을 VSS로 내리고, 나머지 시간에는 PD-CN이 하이인 M23이 OUT을 VSS로 붙잡는다. 캐리 경로와 게이트 라인 부하가 분리되는 것이 핵심이다.When stage n outputs high, the carry passes to the next stage and M21 turns on, charging the gate line toward Vgh. RET from the next stage lets M22 pull OUT to VSS; for the rest of the frame M23 (PD-CN high) holds OUT at VSS. The key is that the carry path is separated from the gate-line load.
검증 방법과 결과Method and results
청구항 1 문장에서 뽑은 넷리스트 초안으로 출력 유닛과 시프트 레지스터 풀업(M3)·리셋(M9)을 구성하고, PU 노드는 이상적 부트스트랩 파형으로 넣었다. 같은 3 kΩ 누설(게이트 라인→0 V)을 발명과 종래 구조에 넣었더니 캐리가 8.01 V 대 5.49 V였다. 결함 행 자체의 게이트 라인은 발명 1.55 V, 종래 3.29 V로 오히려 발명이 낮다. 발명은 '다른 행을 지키는' 구조이지 결함 행을 살리는 구조가 아니다.The outputting unit plus the shift-register pull-up (M3) and reset (M9), drafted from claim 1, were simulated with an ideal bootstrapped PU waveform. With the same 3 kΩ leak (gate line to 0 V) the carry was 8.01 V (invention) vs 5.49 V (prior art). The defective row itself is lower with the invention (1.55 V vs 3.29 V): the structure protects the other rows, not the defective one.
문서와 물리의 차이Text vs physics
[0038]은 M21이 켜지면 OUT이 'Vgh를 출력한다'고 쓰지만, 게이트=IN·소스=Vgh인 NMOS는 소스 팔로워라 OUT은 IN−Vth 이상 오르지 못한다. 시뮬레이션에서 7.05 V(Vgh 8 V)였다. 완전한 Vgh 출력에는 IN의 부트스트랩이나 Vgh보다 높은 IN이 필요한데 청구항에는 없다. 또 도 3 설명은 '도 1의 게이트 구동 장치'의 시프트 레지스터라고 해 종래 도면을 가리킨다.[0038] says OUT 'outputs Vgh' when M21 turns on, but an NMOS with gate = IN and source = Vgh is a source follower, so OUT cannot rise above IN − Vth: 7.05 V for Vgh 8 V in the simulation. A full Vgh output needs IN bootstrapped above Vgh, which the claims do not include. The caption of Fig. 3 also refers to the shift register of Fig. 1, the prior-art drawing.
가정Assumptions
PU는 이상적 PWL, 소자 크기(M3 300 µm, M21 300 µm 등)와 ±8 V는 임의, TFT는 합성 데이터의 산화물 NMOS 카드(25 °C), 결함은 3 kΩ 누설 하나만 봤다.Ideal PWL for PU; sizes (M3 300 µm, M21 300 µm, …) and ±8 V are arbitrary; oxide NMOS card from synthetic data (25 °C); one defect value (3 kΩ) only.
시뮬레이션 준비도Simulation readiness — 4/6
앞의 두 사례에서 넷리스트를 짜기 전에 필요했던 항목이다. ✗ 항목은 직접 가정해야 한다.Items the two case studies needed before a netlist could be written. Each ✗ must be assumed by you.
| 항목Item | 근거Evidence | |
|---|---|---|
| ✓ | 회로도 도면Circuit diagram | 2, 3, 4 |
| ✓ | 타이밍·파형 도면Timing / waveform figure | 5 |
| ✓ | 소자별 단자 연결 서술Per-device terminal connections | 9 문단·청구항 |
| ✓ | 소자 극성·재료Device polarity / material | |
| ✗ | 전원 전압 수치Supply voltage values | |
| ✗ | 소자 크기(W/L)Device size (W/L) |
도면Drawings
이미지를 누르면 확대된다. 휠·핀치로 배율, 끌어서 이동.Click an image to zoom. Wheel / pinch to scale, drag to pan.
추출된 회로 요소Extracted circuit elements
소자 라벨Device labels
전원Supplies
클록Clocks
노드·신호Nodes & signals
전압 수치Voltage values
| 수치 전압 없음No numeric voltages |
이 보고서의 한계Limits of this report
이 보고서는 공보 문서에서 구조를 자동으로 뽑은 것이다. 회로 동작은 시뮬레이션하지 않았다. 특허 내용의 진위를 확인하려면 사례 보고서처럼 도면에서 넷리스트를, 파형도에서 자극 파일을 손으로 만들어 ngspice + Verilog-A TFT 모델로 돌려야 한다.This report is an automatic structural extraction from the publication. The circuit was not simulated. To check whether the patent's claims hold, build the netlist from the drawings and the stimulus from the timing chart by hand, and run them in ngspice with the Verilog-A TFT model, as in the case reports.
시뮬레이션 검증Simulation check
회로 카드는 특허 문장·도면을 보고 사람이 확정한 것이다. 소자 크기·전압·타이밍은 가정이다. TFT 카드는 합성 데이터에서 뽑은 25 °C 값이다.Circuit cards were confirmed by a person against the patent text and drawings. Sizes, voltages and timing are assumptions. TFT cards are 25 °C values fitted to synthetic data.
① 발명 (도 4), 정상 게이트 라인 통과pass
2026-10-20T21:59:07 · ngspice + Verilog-A TFT (LTPS PMOS / oxide NMOS, 25 °C)
| carry | gateline |
|---|---|
| 8.031 | 7.045 |
| 판정 조건Check | 결과Result | ||
|---|---|---|---|
| ✓ | carry > 6 | 8.031 | |
| ✓ | gateline > 6 | 7.045 |
회로 카드Circuit card
# EP2738758B1 FIG.4, normal gate line (no defect): how high does the gate line go through M21? TFT M3 N output pu clk W=300 L=4 # SR pull-up (from claim 1 draft) TFT M9 N vss ret output W=50 L=4 # SR output reset CAP Ccas output 0 0.5p # next stage input + IN of M21 TFT M21 N out output vgh W=300 L=4 # first outputting module TFT M22 N vss ret out W=100 L=4 # second outputting module TFT M23 N vss pd_cn out W=100 L=4 # third outputting module RES Rg out row 2k CAP Cg row 0 20p # no defect V VGH vgh DC 8 V VSS vss DC -8 V CLK clk PULSE -8 8 10.5u 50n 50n 4u 10u V PU pu PWL 0 -8 5u -8 5.05u 8 10.5u 8 10.55u 16 14.5u 16 14.55u 8 15.5u 8 15.55u -8 V RET ret PULSE -8 8 15.5u 50n 50n 4u 1 V PDCN pd_cn PWL 0 8 4.95u 8 5u -8 15.5u -8 15.55u 8 TRAN 20n 30u PROBE V(clk) V(pu) V(output) V(out) V(row) MEAS carry MAX V(output) FROM 10.5u TO 14.5u MEAS gateline MAX V(row) FROM 10.5u TO 14.5u CHECK carry > 6 CHECK gateline > 6
ngspice deck
* generated by patent_site sim.py .options rshunt=1e12 gmin=1e-15 abstol=1e-13 reltol=1e-4 method=gear .model m_m3 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0003 L=4e-06 COV=3e-10 n_m3 output pu clk m_m3 .model m_m9 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=5e-05 L=4e-06 COV=3e-10 n_m9 vss ret output m_m9 .model m_m21 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0003 L=4e-06 COV=3e-10 n_m21 out output vgh m_m21 .model m_m22 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0001 L=4e-06 COV=3e-10 n_m22 vss ret out m_m22 .model m_m23 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0001 L=4e-06 COV=3e-10 n_m23 vss pd_cn out m_m23 c_ccas output 0 5e-13 c_cg row 0 2e-11 r_rg out row 2000 v_vgh vgh 0 DC 8 v_vss vss 0 DC -8 v_clk clk 0 PULSE(-8 8 1.05e-05 5e-08 5e-08 4e-06 1e-05) v_pu pu 0 PWL(0 -8 5e-06 -8 5.05e-06 8 1.05e-05 8 1.055e-05 16 1.45e-05 16 1.455e-05 8 1.55e-05 8 1.555e-05 -8) v_ret ret 0 PULSE(-8 8 1.55e-05 5e-08 5e-08 4e-06 1) v_pdcn pd_cn 0 PWL(0 8 4.95e-06 8 5e-06 -8 1.55e-05 -8 1.555e-05 8) .control set num_threads=1 pre_osdi tft.osdi tran 2e-08 3e-05 set wr_singlescale set wr_vecnames wrdata w.txt v(clk) v(pu) v(output) v(out) v(row) .endc .end
② 발명 (도 4), 게이트 라인 결함 3 kΩ 통과pass
2026-10-20T21:59:08 · ngspice + Verilog-A TFT (LTPS PMOS / oxide NMOS, 25 °C)
| carry | gateline |
|---|---|
| 8.011 | 1.545 |
| 판정 조건Check | 결과Result | ||
|---|---|---|---|
| ✓ | carry > 6 | 8.011 |
회로 카드Circuit card
# EP2738758B1 claim 1 / FIG.4: shift register output (OUTPUT) only drives the cascade and IN of the outputting unit; # the gate line is driven by M21 from Vgh. Gate line has a leakage defect (3 kOhm to 0 V), as in [0005]. TFT M3 N output pu clk W=300 L=4 # SR pull-up (from claim 1 draft) TFT M9 N vss ret output W=50 L=4 # SR output reset CAP Ccas output 0 0.5p # next stage input + IN of M21 TFT M21 N out output vgh W=300 L=4 # first outputting module TFT M22 N vss ret out W=100 L=4 # second outputting module TFT M23 N vss pd_cn out W=100 L=4 # third outputting module RES Rg out row 2k CAP Cg row 0 20p RES Rdef row 0 3k # defective gate line V VGH vgh DC 8 V VSS vss DC -8 V CLK clk PULSE -8 8 10.5u 50n 50n 4u 10u V PU pu PWL 0 -8 5u -8 5.05u 8 10.5u 8 10.55u 16 14.5u 16 14.55u 8 15.5u 8 15.55u -8 V RET ret PULSE -8 8 15.5u 50n 50n 4u 1 V PDCN pd_cn PWL 0 8 4.95u 8 5u -8 15.5u -8 15.55u 8 TRAN 20n 30u PROBE V(clk) V(pu) V(output) V(out) V(row) MEAS carry MAX V(output) FROM 10.5u TO 14.5u MEAS gateline MAX V(row) FROM 10.5u TO 14.5u CHECK carry > 6
ngspice deck
* generated by patent_site sim.py .options rshunt=1e12 gmin=1e-15 abstol=1e-13 reltol=1e-4 method=gear .model m_m3 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0003 L=4e-06 COV=3e-10 n_m3 output pu clk m_m3 .model m_m9 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=5e-05 L=4e-06 COV=3e-10 n_m9 vss ret output m_m9 .model m_m21 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0003 L=4e-06 COV=3e-10 n_m21 out output vgh m_m21 .model m_m22 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0001 L=4e-06 COV=3e-10 n_m22 vss ret out m_m22 .model m_m23 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0001 L=4e-06 COV=3e-10 n_m23 vss pd_cn out m_m23 c_ccas output 0 5e-13 c_cg row 0 2e-11 r_rg out row 2000 r_rdef row 0 3000 v_vgh vgh 0 DC 8 v_vss vss 0 DC -8 v_clk clk 0 PULSE(-8 8 1.05e-05 5e-08 5e-08 4e-06 1e-05) v_pu pu 0 PWL(0 -8 5e-06 -8 5.05e-06 8 1.05e-05 8 1.055e-05 16 1.45e-05 16 1.455e-05 8 1.55e-05 8 1.555e-05 -8) v_ret ret 0 PULSE(-8 8 1.55e-05 5e-08 5e-08 4e-06 1) v_pdcn pd_cn 0 PWL(0 8 4.95e-06 8 5e-06 -8 1.55e-05 -8 1.555e-05 8) .control set num_threads=1 pre_osdi tft.osdi tran 2e-08 3e-05 set wr_singlescale set wr_vecnames wrdata w.txt v(clk) v(pu) v(output) v(out) v(row) .endc .end
③ 종래 (도 1·3), 같은 결함 불통과fail
2026-10-20T21:59:10 · ngspice + Verilog-A TFT (LTPS PMOS / oxide NMOS, 25 °C)
| carry | gateline |
|---|---|
| 5.49 | 3.294 |
| 판정 조건Check | 결과Result | ||
|---|---|---|---|
| ✗ | carry > 6 | 5.49 |
회로 카드Circuit card
# Prior art (EP2738758B1 FIG.1/3): shift register OUTPUT drives the gate line directly and is also the cascade signal. # Same defect (3 kOhm to 0 V on the gate line). TFT M3 N output pu clk W=300 L=4 TFT M9 N vss ret output W=50 L=4 CAP Ccas output 0 0.5p RES Rg output row 2k CAP Cg row 0 20p RES Rdef row 0 3k V VGH vgh DC 8 V VSS vss DC -8 V CLK clk PULSE -8 8 10.5u 50n 50n 4u 10u V PU pu PWL 0 -8 5u -8 5.05u 8 10.5u 8 10.55u 16 14.5u 16 14.55u 8 15.5u 8 15.55u -8 V RET ret PULSE -8 8 15.5u 50n 50n 4u 1 V PDCN pd_cn PWL 0 8 4.95u 8 5u -8 15.5u -8 15.55u 8 TRAN 20n 30u PROBE V(clk) V(pu) V(output) V(row) MEAS carry MAX V(output) FROM 10.5u TO 14.5u MEAS gateline MAX V(row) FROM 10.5u TO 14.5u CHECK carry > 6
ngspice deck
* generated by patent_site sim.py .options rshunt=1e12 gmin=1e-15 abstol=1e-13 reltol=1e-4 method=gear .model m_m3 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=0.0003 L=4e-06 COV=3e-10 n_m3 output pu clk m_m3 .model m_m9 tft CI=0.000345 VTH=0.59477589 U0=11.824568 GAMMA=0.20829257 SS=0.14699661 LAMBDA=0.0098228015 GOFF=2.0128719e-16 POL=-1 TEMPK=298.15 W=5e-05 L=4e-06 COV=3e-10 n_m9 vss ret output m_m9 c_ccas output 0 5e-13 c_cg row 0 2e-11 r_rg output row 2000 r_rdef row 0 3000 v_vgh vgh 0 DC 8 v_vss vss 0 DC -8 v_clk clk 0 PULSE(-8 8 1.05e-05 5e-08 5e-08 4e-06 1e-05) v_pu pu 0 PWL(0 -8 5e-06 -8 5.05e-06 8 1.05e-05 8 1.055e-05 16 1.45e-05 16 1.455e-05 8 1.55e-05 8 1.555e-05 -8) v_ret ret 0 PULSE(-8 8 1.55e-05 5e-08 5e-08 4e-06 1) v_pdcn pd_cn 0 PWL(0 8 4.95e-06 8 5e-06 -8 1.55e-05 -8 1.555e-05 8) .control set num_threads=1 pre_osdi tft.osdi tran 2e-08 3e-05 set wr_singlescale set wr_vecnames wrdata w.txt v(clk) v(pu) v(output) v(row) .endc .end